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MAX1532ETL Rev. A
RELIABILITY REPORT FOR MAX1532ETL PLASTIC ENCAPSULATED DEVICES
May 8, 2003
MAXIM INTEGRATED PRODUCTS
120 SAN GABRIEL DR. SUNNYVALE, CA 94086
Written by
Reviewed by
Jim Pedicord Quality Assurance Reliability Lab Manager
Bryan J. Preeshl Quality Assurance Executive Director
Conclusion The MAX1532 successfully meets the quality and reliability standards required of all Maxim products. In addition, Maxim's continuous reliability monitoring program ensures that all outgoing product will continue to meet Maxim's quality and reliability standards. Table of Contents I. ........Device Description II. ........Manufacturing Information III. .......Packaging Information I. Device Description A. General
The MAX1532 is a dual-phase, Quick-PWMTM, step-down controllers for Intel IMVPTM CPU core supplies. Dual-phase operation reduces input ripple current requirements and output voltage ripple while easing component selection and layout difficulties. The Quick-PWM control scheme provides instantaneous response to fast load-current steps. The MAX1546 includes active voltage positioning with adjustable gain and offset, reducing power dissipation and bulk output capacitance requirements. The MAX1532 is intended for two different notebook CPU core applications: stepping down the battery directly or stepping down the 5V system supply to create the core voltage. The singlestage conversion method allows this device to directly step down high-voltage batteries for the highest possible efficiency. Alternatively, two-stage conversion (stepping down the 5V system supply instead of the battery) at a higher switching frequency provides the minimum possible physical size. The MAX1532 complies with the IMVP-IVTM specifications. The switching regulator features soft-start and power-up sequencing, with the MAX1532 automatically ramping up to the Intel IMVP -IV-specified boot voltage. The MAX1532/MAX1546/MAX1547 also feature independent four-level logic inputs for setting the suspend voltage (S0-S1). The MAX1532 includea output undervoltage protection, thermal protection, and voltage regulator power-OK (VROK) output. When any of these protection features detect a fault, the controller shuts down. Additionally, the MAX1532 includes overvoltage protection. The MA X1532 is available in lowprofile,40-pin 6mm x 6mm thin QFN packages.
V. ........Quality Assurance Information VI. .......Reliability Evaluation IV. .......Die Information .....Attachments
B. Absolute Maximum Ratings Item Rating V+ to GND -0.3V to +30V VCC to GND -0.3V to +6V VDD to PGND -0.3V to +6V SKIP, SUS, D0-D5 to GND -0.3V to +6V ILIM, FB, OFS, CCV, CCI, REF, OAIN+,OAIN- to GND -0.3V to (VCC + 0.3V) CMP, CSP, CMN, CSN, GNDS to GND -0.3V to (VCC + 0.3V) TON, TIME, VROK, S0-S1 to GND -0.3V to (VCC + 0.3V) SHDN to GND (Note 1) -0.3V to +18V DLM, DLS to PGND -0.3V to (VDD + 0.3V) BSTM, BSTS to GND -0.3V to +36V DHM to LXM -0.3V to (VBSTM + 0.3V) LXM to BSTM -6V to +0.3V DHS to LXS -0.3V to (VBSTS + 0.3V) LXS to BSTS -6V to +0.3V GND to PGND -0.3V to +0.3V REF Short-Circuit Duration Continuous Operating Temperature Range -40C to +100C Junction Temperature +150C Storage Temperature Range -65C to +150C Lead Temperature (soldering, 10s) +300C Continuous Power Dissipation (TA = +70C) 40-Pin QFN (6 x 6) 1860mW Derates above +70C 40-Pin QFN 23.2mW/C Note 1: SHDN may be forced to 12V for the purpose of debugging prototype boards using the no-fault test mode, which disables fault protection and overlapping operation.
II. Manufacturing Information A. Description/Function: B. Process: C. Number of Device Transistors: D. Fabrication Location: E. Assembly Location: F. Date of Initial Production: Dual-Phase, Quick-PWM Controller for IMVP CPU Core Power Supplies S12 (Standard 1.2 micron silicon gate CMOS) 11,015 California or Oregon, USA Thailand and USA January, 2003
III. Packaging Information A. Package Type: B. Lead Frame: C. Lead Finish: D. Die Attach: E. Bondwire: F. Mold Material: G. Assembly Diagram: H. Flammability Rating: I. Classification of Moisture Sensitivity per JEDEC standard JESD22-112: 40-Pin QFN (6x6) Copper Solder Plate Silver-filled Epoxy Gold (1.3 mil dia.) Epoxy with silica filler # 05-9000-0383 Class UL94-V0
Level 1
IV. Die Information A. Dimensions: B. Passivation: C. Interconnect: D. Backside Metallization: E. Minimum Metal Width: F. Minimum Metal Spacing: G. Bondpad Dimensions: H. Isolation Dielectric: I. Die Separation Method: 130 x 172 mils Si3N4/SiO2 (Silicon nitride/ Silicon dioxide) Aluminum/Si (Si = 1%) None 1.2 microns (as drawn) 1.2 microns (as drawn) 5 mil. Sq. SiO2 Wafer Saw
V. Quality Assurance Information A. Quality Assurance Contacts: Jim Pedicord (Reliability Lab Manager) Bryan Preeshl (Executive Director) Kenneth Huening (Vice President) 0.1% for all electrical parameters guaranteed by the Datasheet. 0.1% For all Visual Defects.
B. Outgoing Inspection Level:
C. Observed Outgoing Defect Rate: < 50 ppm D. Sampling Plan: Mil-Std-105D VI. Reliability Evaluation A. Accelerated Life Test The results of the 135C biased (static) life test are shown in Table 1. Using these results, the Failure Rate () is calculated as follows: = 1 = MTTF 1.83 192 x 4389 x 48 x 2 (Chi square value for MTTF upper limit)
Temperature Acceleration factor assuming an activation energy of 0.8eV = 22.62 x 10-9 = 22.62 F.I.T. (60% confidence level @ 25C)
This low failure rate represents data collected from Maxim's reliability monitor program. In addition to routine production Burn-In, Maxim pulls a sample from every fabrication process three times per week and subjects it to an extended Burn-In prior to shipment to ensure its reliability. The reliability control level for each lot to be shipped as standard product is 59 F.I.T. at a 60% confidence level, which equates to 3 failures in an 80 piece sample. Maxim performs failure analysis on any lot that exceeds this reliability control level. Attached Burn-In Schematic (Spec. # 06-6131) shows the static Burn-In circuit. Maxim also performs quarterly 1000 hour life test monitors. This data is published in the Product Reliability Report (RR-1M). B. Moisture Resistance Tests Maxim pulls pressure pot samples from every assembly process three times per week. Each lot sample must meet an LTPD = 20 or less before shipment as standard product. Additionally, the industry standard 85C/85%RH testing is done per generic device/package family once a quarter. C. E.S.D. and Latch-Up Testing The PD38-1 die type has been found to have all pins able to withstand a transient pulse of 1500V, per MilStd-883 Method 3015 (reference attached ESD Test Circuit). Latch-Up testing has shown that this device withstands a current of 250mA.
Table 1 Reliability Evaluation Test Results MAX1532ETL TEST ITEM TEST CONDITION FAILURE IDENTIFICATION SAMPLE SIZE NUMBER OF FAILURES
PACKAGE
Static Life Test (Note 1) Ta = 135C Biased Time = 192 hrs. Moisture Testing (Note 2) Pressure Pot Ta = 121C P = 15 psi. RH= 100% Time = 168hrs. Ta = 85C RH = 85% Biased Time = 1000hrs.
DC Parameters & functionality
48
0
DC Parameters & functionality
QFN
77
0
85/85
DC Parameters & functionality
77
0
Mechanical Stress (Note 2) Temperature Cycle -65C/150C 1000 Cycles Method 1010 DC Parameters & functionality 77 0
Note 1: Life Test Data may represent plastic DIP qualification lots. Note 2: Generic Package/Process data
Attachment #1 TABLE II. Pin combination to be tested. 1/ 2/
Terminal A (Each pin individually connected to terminal A with the other floating) 1. 2. All pins except VPS1 3/ All input and output pins
Terminal B (The common combination of all like-named pins connected to terminal B) All VPS1 pins All other input-output pins
1/ Table II is restated in narrative form in 3.4 below. 2/ No connects are not to be tested. 3/ Repeat pin combination I for each named Power supply and for ground (e.g., where VPS1 is VDD, VCC, VSS, VBB, GND, +VS, -VS, VREF, etc). 3.4 a. b. Pin combinations to be tested. Each pin individually connected to terminal A with respect to the device ground pin(s) connected to terminal B. All pins except the one being tested and the ground pin(s) shall be open. Each pin individually connected to terminal A with respect to each different set of a combination of all named power supply pins (e.g., V , or V SS1 SS2 or V SS3 or V CC1 , or V CC2 ) connected to terminal B. All pins except the one being tested and the power supply pin or set of pins shall be open. Each input and each output individually connected to terminal A with respect to a combination of all the other input and output pins connected to terminal B. All pins except the input or output pin being tested and the combination of all the other input and output pins shall be open.
c.
TERMINAL C
R1 S1 R2
TERMINAL A REGULATED HIGH VOLTAGE SUPPLY
S2 C1
DUT SOCKET
SHORT CURRENT PROBE (NOTE 6)
TERMINAL B
R = 1.5k C = 100pf
TERMINAL D Mil Std 883D Method 3015.7 Notice 8
MAXIM
TITLE: BI Circuit: MAX1546/1547 (PD38Z) DOCUMENT I.D. REVISION A PAGE
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